1. Field of the Invention
The present invention relates generally to the field of semiconductor CMOS technology and, more particularly, to high mobility crystalline planes in tri-gate FinFET CMOS technology.
2. Description of the Related Art
The mobility rates of holes and electrons through a p-channel and an n-channel of a p-type field effect transistor (p-FETs) and an n-type field effect transistor (n-FETs), respectively, effects delay. These mobility rates can be a function of the crystalline orientation of the semiconductor used to form the channel region. For example, delay can be minimized in a p-FET by forming the p-channel in a semiconductor having a 110 crystalline orientation which has the highest mobility for holes. Delay can be minimized in an n-FET by forming the channel in a semiconductor having a 100 crystalline orientation which has the highest mobility for electrons. Recent developments in FET technology allow semiconductor planes (e.g., fins) with different crystalline orientations to be formed on the same substrate so that each plane has an optimal mobility for incorporation into a particular type FET (e.g., an n-FET or a p-FET).
U.S. Pat. No. 6,794,718 issued to Nowak et al. on Sep. 21, 2004 and incorporated herein by reference discloses a CMOS structure in which an n-FET and a p-FET are formed on the same substrate. In particular, the structure comprises a double-gated n-FET (e.g., a finFET) having an n-channel in a semiconductor fin with a 100 orientation and double-gated p-FET having a p-channel in a semiconductor fin with a 110 orientation. The two semiconductor fins are formed on the same substrate and positioned with a non-orthogonal, non-parallel orientation with respect to one another (i.e., a chevron structure). However, the method used to form the fins can result in one of the fins having a top surface with a different crystalline orientation. For example, either the fin with the 100 orientation will with have a top surface with a 110 orientation or the fin with the 110 orientation will have a top surface with a 100 orientation. The wafer used to make the fin structure will determine which fin has the top surface with the different orientation.
While a fin having a top surface with a different orientation may be satisfactory for use in a double-gated FET (i.e., a finFET), this differing top surface orientation can affect the performance of a tri-gate MOSFET. Specifically, tri-gate MOSFETs have a similar structure to that of a finFET; however, the fin width and height are approximately the same so that the gate is present on three sides of the fins, including the top surface of the fin and the opposing sidewalls. For a detail discussion of the structural differences between dual-gate finFETs and tri-gate MOSFETs see “Dual-gate (finFET) and Tri-Gate MOSFETs: Simulation and Design” by A Breed and K. P. Roenker, Semiconductor Device Research Symposium, 2003, pages 150–151, December 2003 (incorporated herein by reference). Due to the lower mobility top surface, inversion can occur at the top surface of the fin in the channel region and can cause delay in a tri-gate MOSFET.